The flatness of a semiconductor wafer is a central quality parameter used for assessing the fundamental suitability of the semiconductor wafer as a substrate for producing the most modern generation of electronic components. An ideally flat semiconductor wafer having completely flat side areas opposite one another in parallel fashion would not bring about any focusing difficulties for the stepper during the lithography in the course of producing components. It is therefore endeavored to attain this ideal form as closely as possible. For this purpose, a semiconductor wafer sliced from a crystal undergoes a series of machining steps, wherein, for example, the mechanical machining at the start of the process by means of lapping and/or grinding of the side areas serves for shaping. Subsequent steps such as the etching of the semiconductor wafer and the polishing of the side areas are effected primarily in order to eliminate damage near the surface that has been left behind by the mechanical machining steps, and in order to smooth the side areas. At the same time, these subsequent steps influence the flatness of the semiconductor wafer to a critical extent and all efforts aim as far as possible to retain the flatness obtained by the mechanical machining steps.
A series of standardized parameters are available for the quantitative characterization of the flatness. This also applies, for example, to the region of the edge of the front side of the semiconductor wafer, where front side is usually taken to mean that side of a semiconductor wafer which is used as a basis for the integration of electronic components.
The manufacturers of electronic components endeavor also to include the region of the edge as comprehensively as possible in the usable area FQA, “Fixed Quality Area”. Accordingly, the specified permitted edge exclusion “EE” is becoming ever smaller. Present specifications permit an edge exclusion of only 1 mm.
Unevenness can be described by a SFQR value. The SFQR value denotes the local flatness in a measurement zone having a specific dimensioning, for example, an area of 20 mm×20 mm, to be precise in the form of the maximum height deviation of the front side of the semiconductor wafer in the measurement zone with respect to a reference area having the same dimensioning that is obtained by error square minimization. Partial sites are measurement zones in the edge region which are no longer fully part of the FQA, but the center of which still lies in the FQA. A PSFQR value denotes the local flatness in partial sites, as does an ESFQR value. The latter is based on a more comprehensive metric.
Alongside the local flatness, it is always necessary to also take account of the global flatness of the front side of the semiconductor wafer. Standardized parameters for describing the global flatness are the GBIR value and the SBIR value, which correlates with this value. Both parameters express the maximum height deviation of the front side relative to a rear side—assumed to be ideally flat—of the semiconductor wafer and differ in that the FQA is used for calculation in the case of the GBIR value, while the area restricted to the measurement zone is used for calculation of the SBIR value.
Definitions of the abovementioned parameters and descriptions of methods for measuring said parameters are contained in the relevant SEMI standards, in particular in the M1, M67 and M1530 standards.
It is known that double-side, simultaneously effected polishing of the semiconductor wafer, hereinafter referred to as “DSP polishing”, favorably influences the local flatness. The material removal in the course of a DSP polishing, amounting to 5 μm to 15 μm per side, is significantly higher than the material removal sought with a CMP polishing (“Chemical Mechanical Polishing”). A machine suitable for DSP polishing is described, for example, in DE 100 07 390 A1. During the DSP polishing, the semiconductor wafer lies in a cutout provided for it in a carrier acting as a guide cage, and between an upper and a lower polishing plate. At least one polishing plate and the carrier are rotated, and the semiconductor wafer moves, with a polishing agent being supplied, on a path predetermined by a rolling curve relative to the polishing plates covered with polishing cloth. The polishing pressure with which the polishing plates press onto the semiconductor wafer and the duration of the polishing are parameters that crucially codetermine the material removal brought about by the polishing.
US 2002/0055324 A1 describes a DSP polishing which is terminated by replacing the polishing agent with a stopping reagent at the end of the polishing. The polishing agent described therein has a typical composition. It contains, for example, silicon dioxide (SiO2) in an amount of 1 to 10% by weight and an alkaline component in an amount of 0.01 to 10% by weight.
US2008/0070483 A1 describes a method comprising two successive polishing steps that are each carried out as DSP polishing. The first polishing step involves polishing a semiconductor wafer until the difference between the thickness of the semiconductor wafer in the center of the semiconductor wafer and the thickness of the carrier is negative. A semiconductor wafer having a concave form deviating from the ideal form is obtained in this way. What is advantageous about the method is that the local flatness in the edge region of the front side of the semiconductor wafer has a PSFQR value of not more than 35 nm and thus lies in a range regarded as favorable as early as after the first polishing step. What is disadvantageous about the method is that a second DSP polishing is required in order to bring the global flatness of the front side of the semiconductor wafer to an SBIR value of less than 100 nm.